1. Field of the Invention
This invention relates to an exclusive-or gate circuit suitable for use as a parity bit generator in an integrated circuit, and in particular, to an exclusive-or gate with increased packing density, increased speed and lower power consumption over prior art circuits and which is easier to manufacture than prior art circuits.
2. Description of the Prior Art
Exclusive-or gates with two input leads generate a logical "0" output signal if two input signals have the same state (logical "0" or logical "1") and generate a logical "1" output signal if two input signals have different states. Successive stages of exclusive-or circuitry can be combined to generate an exclusive-or output signal for any number of input signals with the result that a logical "0" is generated if an even number of inputs are logical "1" and a logical "1" is generated if an odd number of inputs are logical "1".
Circuits for generating exclusive-or logic are well-known. The two-input exclusive-or circuit of conventional prior art shown in FIG. 1a must generate an inverted signal from the signal from each input terminal and combine the inverted signal from one terminal with the noninverted signal from the other terminal, in a double-emitter transistor, and then combine the signals from the two double-emitter transistors to generate a single exclusive-or signal.
According to the prior art, the number of stages needed to generate a single exclusive-or output signal is the base-2 logarithm, rounded upward, of the number of input terminals to be used.
A typical inverter circuit of the prior art is shown within the smaller dotted lines of FIG. 1a. This inverter requires large silicon area for its five semiconductor components and four resistors and introduces three propagation gate delays into the circuit associated with the inversion of a transistor. In addition, the exclusive-NOR circuitry, according to the prior art, as shown in section 10 of FIG. 1a, continuously draws current from the first to second voltage potentials (i.e., from supply voltages to ground) or from the first potential to a low-state input terminal.
This prior art exclusive-or circuit feeds the inverted signal from first input terminal A and the noninverted signal from a second input terminal B to corresponding terminals of the dual emitters of a transistor Q9 operating as a diode. Transistor Q9 has its base connected through a resistor to a first voltage potential and its collector, which is shorted to its own base, connected to the base of a further transistor Q11. Likewise, this prior art circuit feeds the inverted signal from the second input terminal, B, and the noninverted signal from the first input terminal, A, to corresponding terminals of the dual emitters of transistor Q10, also connected as a diode. Transistor Q10 also has its base connected through a resistor to a first voltage potential and its collector, which is shorted to its own base, connected to the base of a further transistor Q12. The emitters of these further transistors Q11 and Q12 are connected to a second voltage potential (shown as ground) through a diode Q13 which provides a potential difference to control the turn-on-turn-off level, and the collectors of Q11 and Q12 are connected to a phase splitter transistor Q14 which controls the operation of pull-up and pull-down transistors Q15, Q16 to the output terminal.
The circuit of FIG. 1a draws power from the high voltage potential to the low potential through transistors Q11 or Q12 if one or both are on, and through transistors Q9 and/or Q10 continuously (i.e., whether or not signals A and B are the same or different).
A variety of configurations for controlling the output signal from the phase splitter transistor are known and used. Two arrangements are shown in the accompanying figures, one in FIGS. 1, 2, and 4 and a second in FIG. 3.
If a third input signal is to be used, the output signal from the circuit shown in FIG. 1 is generated for two of the input signals and combined with a third input signal in a complete second stage, to generate a signal exclusive-or signal. This arrangement doubles the switching time of a two-input circuit, by the addition of a complete second stage. For four input signals, two groups are formed generating two first stage output signals which are combined in a second stage to generate a single output signal. Five through eight input signals employ a third stage, and so on, the number of stages being equal to the base-2 logarithm, rounded upward to the next integer, of the number of input signals to be simultaneously processed. As noted in FIG. 7, the time delay from input to output is typically 5 nanoseconds for a 2 input circuit and 20 nanoseconds for a 16 input circuit.
Another circuit of the prior art is shown in FIG. 1b. In FIG. 1b transistors Q3 and Q4 can comprise standard NPN transistors or Schottky clamped NPN transistors. As shown in FIG. 1b the collector of transistor Q3 is connected through a pull-up resistor to voltage supply V.sub.ss. The emitter of transistor Q3 is connected to the emitter of transistor Q2 which has its base connected through a resistor to V.sub.ss. The emitter of Q2 is also connected to input terminal B while the collector of transistor Q2 is connected to the base of switching transistor Q4. The collector of Q4 is connected to the collector of Q3 and to a node C. The emitter of transistor Q4 is connected to the emitter of a second switching transistor Q1 which has its base connected through a resistor to V.sub.ss and is also connected to input terminal A. The collector of switching transistor Q1 is connected to the base of Q3.
In operation, a high level signal on input terminal A and a low level signal on input terminal B results in transistor Q1 being biased off and transistor Q2 being biased on. Transistor Q3 is then turned on by the high level voltage on its base and the low level signal on input terminal B. The low level signal on the emitter of Q2 is applied to the base of transistor Q4 thereby biasing transistor Q4 off. If both input signals A and B are on or off, transistors Q3 and Q4 will not have their base-emitter junctions forward biased and will therefore be off. The result is that the output signal on output lead C represents an exclusive-NOR function. One problem with this circuit of the prior art is that the voltage on the collectors of switching transistors Q3 and Q4 makes the full swing from supply voltage V.sub.ss to almost ground. This makes the circuit much slower than desire for high speed VLSI applications. Also, connecting the emitters of Q3 and Q4 to the input terminals B and A respectively results in the voltages on the emitters of these two transistors swinging between the high and low levels of the input signals on terminals A and B. This again slows down the operation of the circuit. Furthermore, all four transistors and accompanying resistors must be replicated for multiple inputs.